1. Field of the Invention
This invention relates to a drive device for driving a display apparatus and a method of driving a display apparatus, and more particularly to a drive device for a display apparatus which is capable of gray-scale display by means of amplitude modulation and also to a method of driving such a display apparatus. In this specification, a display apparatus using a matrix liquid crystal display apparatus will be described as a typical example of a display apparatus, but this invention can also be applied to drive circuits for other types of display apparatuses such as electroluminescent (EL) display apparatus and plasma display apparatus.
2. Description of the Prior Art
FIG. 20 shows a matrix liquid crystal display apparatus of the prior art. The matrix liquid crystal display of FIG. 20 employs a TFT liquid crystal panel 100 comprising thin-film transistors (TFT) as the switching elements for driving pixel electrodes 103. The TFT liquid crystal panel 100 further comprises n (numbered from 0 to n-1) scanning electrodes 101 positioned parallel to each other and m (numbered from 0 to m-1) signal electrodes 102 positioned parallel to each other and perpendicularly intersecting the scanning electrodes 101. TFTs 104 for driving the pixel electrodes 103 are located in the vicinity of the intersections of the scanning electrodes 101 and the signal electrodes 102. One horizontal scanning line is composed of m pixel electrodes 103 arranged in a row. Counter electrodes 105 which are respectively opposite to the pixel electrodes 103 are formed. A plurality of counter electrodes are shown in FIG. 20, but actually they are consist of one conductive layer formed in common to all of the pixel electrodes 103. A fixed voltage v.sub.c is impressed on the counter electrodes 105.
The TFT liquid crystal panel 100 is driven by a drive device containing a source driver 200 and gate driver 300. The source driver 200 and gate driver 300 are connected to the signal electrodes 102 and the scanning electrodes 101, respectively, of the TFT panel 100. The source driver 200 samples an input analog video signal or video signal, and holds it. The held signal is supplied to the signal electrodes 102. The gate driver 300 outputs scanning pulses to the scanning electrodes 101 in sequence. The timing signal and other signals input to the gate driver 300 and source driver 200 are supplied from a control circuit 400.
With reference to FIG. 21, the source driver 200 will be described in more detail. The source driver 200 comprises a shift register 210, sample and hold circuits 220 and output buffers 230. In the shift register 210, shift pulses input from the control circuit 400 are shifted in accordance with the shift clock, and sampling pulses are output sequentially to lines B.sub.1, B.sub.2, ..., B.sub.i, ..., B.sub.m. In conjunction with this, analog switches ASW1(1), ..., ASW1(i), ..., ASW1(m) become closed in sequence, and sampling capacitors 221 are charged in sequence up to the instantaneous amplitude v(i, j) of the input analog video signal. Here, v(i, j) is the instantaneous amplitude of an analog video signal to be written to the pixel electrode 103 corresponding to the intersection of the ith signal electrode and jhe scanning electrode of the TFT liquid crystal panel 100. In this way, after video signals of one horizontal scanning period are sampled by the sample and hold circuit 220, an output pulse OE is input, and the video signals are transferred from the sampling capacitors 221 to the holding capacitors 222. The video signal held by the holding capacitors 222 are output to the signal electrodes 102 via the output buffers 230.
FIG. 22 diagrammatically shows waveforms of the input and output signals in the source driver 200. In FIG. 22, v(C.sub.SPL (i)), v(C.sub.H (i)) and v.sub.S (i) denote the voltage of the ith sampling capacitor 221, the voltage of the ith holding capacitor 222 and the output voltage of the ith output buffer 230, respectively.
FIG. 23 shows another matrix liquid crystal display device of the prior art in which a TFT liquid crystal panel 100 further comprises supplemental capacitance electrodes 106. The equivalent circuit of the pixels in the TFT liquid crystal panel 100 shown in FIG. 23 is illustrated in FIG. 24. As shown in FIG. 24, in addition to the pixel capacitance C.sub.LC formed between the pixel electrode 103 and the counter electrode 105, a supplemental capacitance C.sub.S is formed between the pixel electrode 103 and the supplemental capacitance electrode 106. In the TFT liquid crystal panel 100, the waveform of the AC signal applied to a liquid crystal pixel is asymmetric even when the signal electrodes 102 are AC-driven, and this results in the formation of polarized electric fields in the liquid crystal pixels, which results in the deterioration of the liquid crystal pixels and reduces their reliability. The addition of a supplemental capacitance is aimed at improving this kind of problem and reducing flicker.
Generally, one of the electrodes of the supplemental capacitance C.sub.S is formed by a part of the pixel electrode 103. The other electrode (i.e., supplemental capacitance electrodes 106) of the supplemental capacitance C.sub.S may be connected by either of the following two methods.
In the first method, as shown in FIG. 23, the supplemental capacitance electrode 106 corresponding to the jth scanning electrode 101 is connected electrically to the adjacent (j-1)th scanning electrode 101. The supplemental capacitance electrode 106 corresponding to the 0th (j=0) scanning electrode 101 is connected to the counter electrode 105. This method is referred to as the CS on-gate method.
In the second method, as shown in FIG. 25, the supplemental capacitance electrode 106 is connected electrically to the counter electrode 105. In this case, the voltage v.sub.x of the supplemental capacitance electrode 106 is equal to the voltage v.sub.c of the counter electrode 105.
In the second method, fetch bus lines for connecting the supplemental capacitance electrodes 106 to the counter electrodes 105 must be wired parallel to the scanning electrodes 101, thus causing a problem with reduced pixel areas. In the first method, however, such fetch bus lines can be realized by the gate electrodes, so this method is advantageous with respect to the improvement of pixel areas.
The so-called "analog video signal sampling method" drive circuits described above present the following problems (1) to (4) when attempts are made to increase the size or improve the resolution of a display panel such as the above-mentioned TFT liquid crystal panel 100.
(1) In a drive device which samples the amplitude of an analog video signal, the accuracy in the amplitude v(i, j ) of a sampled video signal is determined by the time constant established by the on-resistance R.sub.ON of the closed analog switch ASW1(i) and the capacitance C.sub.SPL of the sampling capacitor 221. Hence, the above-mentioned time constant must be selected so that the frequency band of the video signal is not narrowed by the sampling. More specifically, assuming the frequency at which the signal level drops by 3 dB is expressed as f(-3 dB) Hz in the frequency characteristic of the input analog video signal, then the condition in the following equation must be satisfied. ##EQU1##
As the capacity and resolution of display panels (TFT liquid crystal panel 100) are increased, the frequency band becomes wider, which requires faster sampling, so a low R.sub.ON and small C.sub.SPL are required to satisfy the equation above.
The charges in the sampling capacitors 221 are distributed to the holding capacitors 222 by the output pulse OE, and the voltage of the holding capacitor 222 of the capacitance C.sub.H becomes as follows. ##EQU2## When C.sub.H (i) &lt;&lt;C.sub.SPL (i), therefore, v(C.sub.H (i)) is approximately equal to v(i, j). It can be seen that there is a limit to the minimization of the capacitance C.sub.SPL in order to minimize amplitude attenuation due to charge distribution from the sampling capacitors 221 to the holding capacitors 222. Further, in order to suppress deterioration or irregularity of the input/output linearity due to dispersion during production in the on-resistance R.sub.ON as well as in the capacitances C.sub.SPL and C.sub.H, the capacitance C.sub.SPL cannot be made very small. As this indicates, there is a limit to the minimization of the capacitance of the sampling capacitors 221, so it is difficult to greatly widen the frequency band of the input video signal. This problem becomes an obstacle to increasing the capacity of a display panel.
(2) Analog video signals are supplied to the source driver 200 via the bus line as shown in FIG. 21, and as the capacity and resolution of a display panel are increased, the frequency band of the video signal becomes wider and the distribution capacity of the bus line increases. This results in the necessity of a wideband amplifier in the circuit supplying video signals, and increases the cost of production.
(3) When bus lines for supplying multiple analog video signals are arranged in a color display apparatus in which RGB video signals are used, as the capacity and resolution of the display panel are increased, the above-mentioned wideband amplifier is required to have extremely high signal quality in that there can be no phase differences between the multiple video signals and no dispersion in the amplitude characteristics or frequency characteristics.
(4) Unlike the displaying in a CRT, in drive circuits for matrix display devices, analog video signals are sampled according to a clock signal and displayed in pixels arranged in a matrix. Because delays in the drive device including delays in the bus lines cannot be avoided, it is extremely difficult to accurately establish the sampling position for the analog video signals. Particularly, when displaying on a matrix display apparatus a computer graphic image in which the relationship between video signals and pixel addresses is clearly defined, though in theory it should be possible to perfectly reproduce computer-generated images on the display panel, shift in the image display position, bleeding of the image, etc., due to delays in the drive system and deterioration of the frequency characteristics cannot be avoided in drive circuits using an analog video signal sampling method of the prior art.
Further, the operating voltage of the source driver in a drive device of the prior art presents problems concerning source drivers of the prior art which comprise shift registers, counters and other logic circuits which operate on low voltages, and sample and hold circuits, level shifters, output buffers and other intermediate-voltage circuits which operate at voltages higher than the logic circuits. The integration of such circuits with different operating voltages into a monolithic LSI device requires design rules and production processes suitable for the intermediate-voltage circuits. In the prior art, consequently, the increase of the operating speed of a logic circuitry is hindered, and it is difficult to attain high levels of large-scale integration, reduce costs and achieve low power consumption.